The present invention relates to a system for transmitting two types of signal by orthogonal modulation, or more in particular to a digital signal transmission system comprising an orthogonal modulation transmission unit and an orthogonal demodulation receiving unit having a digital configuration.
In recent years, a signal transmission system of orthogonal modulation type such as QPSK or QAM scheme has been employed for improving the transmission rate in the digital radio communication for mobile units and terrestrial communication. The orthogonal modulation scheme is for transmitting two types of signals by orthogonal modulation using two types of mutually orthogonal carriers expressed as
cos(2xcfx80xc3x97fxe2x80x2cxc3x97t)
and
sin(2xcfx80xc3x97fxe2x80x2cxc3x97t)
where t is the time and fxe2x80x2c the carrier frequency.
The conventional digital signal transmission system of orthogonal modulation type has employed an orthogonal modulator/demodulator circuit mainly using a mixer of analog configuration for the apparent reason of its low cost and small circuit size.
The conventional signal transmission system using this orthogonal modulator/demodulator circuit of analog type will be explained with reference to FIGS. 19 and 20.
First, FIG. 19 shows an example of a conventional transmission circuit of orthogonal modulation type. The information code input from an input terminal 1 is converted into two types of baseband digital signals Id(n), Qd(n) by a transmission signal processing circuit 2 and then applied to an orthogonal modulator 3, where n is an integer not less than 1 indicating the order of the clock signal pulses.
The signals Id(n), Qd(n) input to the orthogonal modulator 3 are converted into analog signals by D/A converters 4i, 4q, respectively. Then, the transmission bandwidth of signals is limited to a predetermined value B by LPFs (low-pass filters) 5i, 5q of analog configuration.
The signals I(t), Q(t) output from the LPFs 5i, 5q are input to a mixer 6 where they are orthogonally modulated in analog fashion by the operation according to equation (1) below.
D(t)=I(t)xc3x97cos(2xcfx80xc3x97fcxc3x97t)+Q(t)xc3x97sin(2xcfx80xc3x97fcxc3x97t)xe2x80x83xe2x80x83(1)
The signal D(t) thus orthogonally modulated is input to a BPF (bandpass filter) 7 where the unrequited component generated in the mixer 6 is removed. The output signal of the BPF 7 is supplied to an up converter 8 where it is converted to a carrier signal of a still higher frequency fxe2x80x2c. The high-frequency transmission signal is transmitted from an antenna 9.
FIG. 20 shows an example of a conventional receiving circuit of orthogonal demodulation type. The signal received by an antenna 10 is restored to the original orthogonal modulation signal D(t) by a down converter 11.
The orthogonal modulation signal D(t) supplied to an orthogonal demodulator 13 is input to a mixer 14 and converted into a signal of a carrier frequency fc. The mixer 14 processes the signal D(t) in two ways by equations (2) and (3) shown below, and orthogonally demodulates the two types of signals I(t), Q(t) in analog fashion using the orthogonality of the trigonometric function.
I(t)=D(t)xc3x97cos(2xcfx80xc3x97fcxc3x97t)xe2x80x83xe2x80x83(2)
Q(t)=D(t)xc3x97sin(2xcfx80xc3x97fcxc3x97t)xe2x80x83xe2x80x83(3)
The two signals I(t), Q(t) orthogonally demodulated in this way have the unrequited components thereof removed by the analog LPFs 15i, 15q, respectively. The signals I(t), Q(t) are converted into digital signals Id(n), Qd(n) by the A/D converters 16i, 16q, respectively, and supplied to a receiving signal processing circuit 17.
The receiving signal processing circuit 17 demodulates the two digital input signals Id(n), Iq(n), and outputs the resulting information code from an output terminal 18.
In the conventional analog modulation system described above, the two types of carrier signal used for orthogonal modulation and demodulation, i.e. the two carrier signals expressed by xe2x80x9ccosxe2x80x9d and xe2x80x9csinxe2x80x9d in FIGS. 19 and 20, if insufficient in orthogonality (accuracy of 2xcfx80 in phase difference), develop inter-code interference between the two types of components and increases the error rate of the demodulated code, resulting in a deteriorated communication quality.
In view of this, in the prior art, a mixer of analog configuration regulated to high accuracy is used so that the orthogonal (phase difference) error between the two reference carrier waves assumes a sufficiently small value of 1 degree or less.
The conventional system described above fails to take digitization into consideration and poses the problem of difficulty of improving the performance thereof.
Specifically, in recent years, schemes such as 64QAM or OFDM with a large number of points more than the conventional BPSK and QPSK schemes have come to be employed. These schemes require a still higher accuracy of orthogonality. The analog technique, however, has its own limit of improving the orthogonality accuracy and therefore is difficult to improve the performance of the transmission system.
In view of this, the inventors have studied a digital orthogonal modulator and a digital orthogonal demodulator in which orthogonal modulation and orthogonal demodulation are performed by digital signal processing in order to secure a sufficiently high accuracy required for orthogonality. An example will be explained with reference to FIGS. 21 and 22.
First, the digital orthogonal modulator of FIG. 21 is a digital version of the orthogonal modulator 3 of analog configuration shown in FIG. 19. In similar fashion, the digital orthogonal demodulator of FIG. 22 is a digital version of the orthogonal demodulator 13 of analog configuration shown in FIG. 20. The circuits other than the orthogonal modulator and the orthogonal demodulator are the same as those of FIGS. 19 and 20. Therefore, the configuration and operation of the orthogonal modulator and the orthogonal demodulator will be mainly described below.
First, typical signal waveforms of the first digital signal Id(n) and the second digital signal Qd(n) of a sampling frequency fd supplied from the transmission signal processing circuit 2 are illustrated in FIGS. 23(a), (b).
In FIGS. 23(a), (b), the solid curve represents the signal waveform of the I signal before sampling; and the dashed curve represents the signal waveform of the Q signal before sampling. The corresponding sampling signals are also indicated by solid and dashed arrows, respectively.
Of all the signals applied to the digital orthogonal modulator shown in FIG. 21, the first digital signal Id(n) is converted to a signal Ixe2x80x2d4(m) of a quadruple sampling frequency 4xc3x97fd by a first quadruple sampling converter 19i in such a manner that three zeros are inserted between the nth sampling value Id(n) and the (n+1)th sampling value Id(n+1) as shown in FIG. 23(c), where m is an integer representing the order of the clock signal for the quadruple sampling operation.
The signal Ixe2x80x2d4(m) thus converted, as shown typically in FIG. 24, contains the unrequited harmonic components 20. In FIG. 24, the hatched portions show the bands of the required signal information components.
The digital LPF 21i, like the conventional LPF 5i shown in FIG. 19, limits the signal Ixe2x80x2d4(m) to the bandwidth B while at the same time removing the unrequited harmonic components 20.
As a result, the signal waveform of the output signal Id4(m) of the digital LPF 21i assumes a sampling waveform with zeros filled between the signals as shown in FIG. 23(e).
This is also the case with the second signal Qd(n). As shown in FIG. 23(d), the second signal Qd(n) is converted into a signal Qxe2x80x2d4(m) of a quadruple frequency 4xc3x97fd by a second quadruple sample converter 19q, limited to the bandwidth B by a digital LPF 21q, and as shown in FIG. 23(f), converted into the signal Qd4(m) with zeros filled therebetween.
Assume that the carrier frequency fc of the orthogonal modulation signal is set to fd in this way. Equation (1) indicated above as an operation formula for orthogonal modulation can be expressed as
Dd4(m)=Id4(m)xc3x97cos(2xcfx80xc3x97m/4)+Qd4(m)xc3x97sin(2xcfx80xc3x97m/4)xe2x80x83xe2x80x83(4)
In equation (4), the term on the right side containing xe2x80x9ccosxe2x80x9d assumes values 1 and xe2x88x921 alternately when m is an even number including zero, and assumes zero when m is an odd number.
The term on the right side containing xe2x80x9csinxe2x80x9d, on the other hand, assumes the values of 1 and xe2x88x921 alternately when m is an odd number and assumes zero when m is an even number including zero.
Therefore, equation (4) can be expressed sequentially in accordance with m, as follows.
            m              =                      0        →                  Dd4          ⁡                      (            0            )                                      =                      Id4        ⁡                  (          0          )                                m              =                      1        →                  Dd4          ⁡                      (            1            )                                      =                      Qd4        ⁡                  (          1          )                                m              =                      2        →                  Dd4          ⁡                      (            2            )                                      =                      -                  Id4          ⁡                      (            2            )                                          m              =                      3        →                  Dd4          ⁡                      (            3            )                                      =                      -                  Qd4          ⁡                      (            3            )                                          m              =                      4        →                  Dd4          ⁡                      (            4            )                                      =                      Id4        ⁡                  (          4          )                                m              =                      5        →                  Dd4          ⁡                      (            5            )                                      =                      Qd4        ⁡                  (          5          )                                        xe2x80x83                    ⋮                      xe2x80x83                    ⋮                      xe2x80x83            
Actually, therefore, the orthogonal modulation can be carried out and the orthogonal modulation signal Dd4(m) as shown by the signal waveform of FIG. 23(g) can be produced by sequentially switching the signals Id4(m), Qd4(m) and signals of opposite polarities xe2x88x92Id4(m), xe2x88x92Q4d(m) without executing the multiplication of equation (4).
The digital orthogonal modulator of FIG. 21 uses a digital orthogonal modulation circuit 22 operating according to this method. As shown in FIG. 21, two polarity inverting circuits 22i, 22q and a cyclic switch 22s operating at a frequency fc (=4xc3x97fd) are used. The signals Id4(m) and Qd4(m) are converted into polarity inverted signals xe2x88x92Id4(m) and xe2x88x92Qd4(m), respectively, by the polarity inverting circuits 22i and 22q. The signals Id4(m), Qd4(m), xe2x88x92Id4(m), xe2x88x92Qd4(m) are extracted selectively sequentially by the clock signal of frequency fc through the switch 22s, thereby producing an orthogonal modulation signal Dd4(m) shown in the waveform diagram of FIG. 23(g).
The orthogonal modulation signal Dd4(m) output from the digital orthogonal modulation circuit 22 is then converted into an analog signal by a D/A converter 24. The analog orthogonal modulation signal D(t) with the unrequited harmonic components thereof removed by the BPF 25 is output from the digital orthogonal modulator.
In this process, the two digital LPFs 21i, 21q are required to have the same characteristic.
It is common practice, therefore, to employ digital LPFs having a nonrecursive (FIR: finite impulse response) type circuit configuration and the same tap coefficient, as shown in FIG. 25.
The digital LPF shown in FIG. 25 includes a shift register 26, memories 27-1, 27-2, . . . , 27-H, multiplier circuits 28-1, 28-2, . . . , 28-H and a xcexa3 (summing) circuit 29.
The shift register 26 includes multiple stages of concatenated memory cells for sequentially transferring and storing input serial signals Ixe2x80x2d4(p+1), Ixe2x80x2d4(p+2), . . . , Ixe2x80x2d4(p+H), stage by stage, in response to each clock pulse of frequency 4xc3x97fd. The memories 27-1, 27-2, . . . , 27-H function to store H tap coefficients C1, C2, . . . , CH required for limiting the bandwidth to B. In the above description, p is an arbitrary integer.
The shift register 26 executes the operation of equation (5) below for each clock pulse using the tap coefficient values stored in the memories 27-1, 27-2 and so forth, and sequentially outputs the calculated values Id4(p).
Id4(p)=C1xc3x97Ixe2x80x2d4(p+1)+C2xc3x97Ixe2x80x2d4(p+2)+C3xc3x97Ixe2x80x2d4(p+3)+ . . . + . . . +CHxc3x97Ixe2x80x2d4(p+H)xe2x80x83xe2x80x83(5)
In the process, the H multiplier circuits 28-1, 28-2, . . . , 28-H multiply the tap coefficients C1, . . . , CH by the signals values Ixe2x80x2d4(p+1), . . . , Ixe2x80x2d4(p+H). Further, the xcexa3 circuit 29 includes a plurality of adder circuits and outputs the total sum of the values C1xc3x97Ixe2x80x2d4(p+1) to CHxc3x97Ixe2x80x2d4(p+H) multiplied in the multiplier circuits 28-1 to 28-H. In this way, the multiplier circuits 28-1 to 28-H function as a digital LPF.
Now, the digital orthogonal demodulator of FIG. 22 will be explained. This demodulator carries out orthogonal demodulation by processing the signals in substantially reverse way to the digital orthogonal modulator of FIG. 21.
In FIG. 22, the orthogonal modulation signal D(t) output from a down converter 11 (FIG. 20) has the unrequited frequency components thereof removed by the BPF 30. The signal D(t) is sampled at the sampling frequency of 4xc3x97fd by the A/D converter 31 and thus converted into a digital orthogonal modulation signal Dd4(m).
The orthogonal modulation signal Dd4(m) thus sampled has a signal waveform as shown in FIG. 26(a) which is identical to that of FIG. 23(g).
Assume that the carrier frequency fc of the orthogonal modulation signal is set to fd. Equations (2) and (3) shown as operation formulae for orthogonal demodulation are expressed as equations (6) and (7), respectively.
Id4(m)=Dd4(m)xc3x97cos(2xcfx80xc3x97m/4)xe2x80x83xe2x80x83(6)
Qd4(m)=Dd4(m)xc3x97sin(2xcfx80xc3x97m/4)xe2x80x83xe2x80x83(7)
Then, as in equation (4) for the digital orthogonal modulator shown in FIG. 21, the orthogonal demodulation can be performed with a simple circuit configuration.
Specifically, equation (6) including xe2x80x9ccosxe2x80x9d assumes values of 1 and xe2x88x921 alternately when m is an even number including zero, and assumes zero when m is an odd number. Equation (7) including xe2x80x9csinxe2x80x9d, on the other hand, assumes values of 1 and xe2x88x921 alternately when m is an odd number and zero when m is an even number including zero.
First, equation (6) assumes the following values sequentially according to m.
xe2x80x83m=0xe2x86x92Dd4(0)=Id4(0)
m=1xe2x86x92Dd4(1)=0
m=2xe2x86x92Dd4(2)=xe2x88x92Id4(2)
m=3xe2x86x92Dd4(3)=0
Then, equation (7) assumes the following values also sequentially according to m.
m=0xe2x86x92Dd4(0)=0
m=1xe2x86x92Dd4(1)=Qd4(1)
m=2xe2x86x92Dd4(2)=0
m=3xe2x86x92Dd4(3)=xe2x88x92Id4(3)
m=4xe2x86x92Dd4(4))=0
In this case, too, the orthogonal demodulation can be accomplished by sequentially switching and independently extracting the signals Id4(m), Qd4(m) and polarity-inverted signals xe2x88x92Id4(m), xe2x88x92Qd4(m) without directly executing the multiplication of equations (6) and (7). Thus, the orthogonal demodulation signals Id4(m) and Qd4(m) are obtained as shown in FIGS. 26(b), (C).
FIG. 22 shows a digital orthogonal demodulator using a digital orthogonal demodulation circuit 32 operating according to the above-mentioned method. As shown in FIG. 22, this digital orthogonal demodulator includes two polarity inverting circuits 32i, 32q and cyclic switches 32si, 32sq operating at the frequency of fc (=4xc3x97fd).
The signal Dd4(m) from the A/D converter 31 is output as a polarity-inverted signal xe2x88x92Dd4(m) by the polarity inverting circuits 32i, 22q. These signals are sequentially alternated between 0 (35i, 35q) and Dd4(m), xe2x88x92Dd4(m) for each clock of the frequency fc and selectively output, thereby producing the orthogonal demodulation signals Id4(m), Qd4(m) as shown in FIGS. 26(b), (c).
In this way, the signal Id4(m) output from the digital orthogonal demodulation circuit 32, as shown in FIG. 26(b), assumes a waveform containing a 0 value for each sampling signal.
This portion of 0 value is interpolated by the digital LPF 33i as shown in FIG. 26(d). The signal of FIG. 26(d) is sampled at the sampling frequency fd by the 1/4 sampling converter 34i thereby to output the signal Id(n) orthogonally demodulated as shown in FIG. 26(f).
In similar fashion, the signal Qd4(m) output from the digital orthogonal demodulation circuit 32, as shown in FIG. 26(c), assumes a waveform containing a 0 value for each sampling signal. The signal Qd4(m) has the 0 value portion interpolated by the digital LPF 33q as shown in FIG. 26(e). The signal of FIG. 26(e) is then resampled by the 1/4 sample converter 34q thereby to output the signal Qd(n) orthogonally demodulated as shown in FIG. 26(g).
As shown in FIG. 25, a nonrecursive (FIR type) circuit having the same coefficient values as the digital orthogonal modulator described with reference to FIG. 21 is used as the digital LPFs 33i and 33q. 
The nonrecursive digital filter used in this case requires a considerable number of adder circuits and multiplier circuits.
The multiplier circuits, which assumes a considerable circuit size, are desirably as few as possible.
In the cases of FIGS. 21 and 22 which use a nonrecursive digital LPF of FIG. 25, however, many multiplier circuits are required leading to an extremely large circuit size. An increased size of the multiplier circuits is indicative of an increased number of taps of the digital filter. In other words, as many taps as multiplier circuits are required. In forming a digital filter on a integrated circuit, an increased number of multiplier circuits and an increased number of taps bring about an increased space of the integrated circuit, resulting in an increased manufacturing cost of the filter. The steeper the frequency cutoff characteristic required of the LPF, the more taps (multiplier circuits) are required. In the case of an orthogonal frequency division multiplexing (OFDM) modulation constituting one of the orthogonal modulation schemes, for example, the occupied bandwidth is fully utilized. For the transmission signal not to leak to adjacent other frequency bands, therefore, a digital LPF of at least about 50 taps is required.
Since 50 or more taps are required for the digital LPF, the transmission system requires twice as many multiplier circuits, or about 100 multiplier circuits. This is because two LPFs are used for each tap.
The nonrecursive digital LPF in the receiving system also requires as many multiplier circuits. Thus, a total of about 200 multiplier circuits are required for the transmission system and the receiving system combined.
As long as the information transmission rate remains low, the use of the multiplier circuits by time division can reduce the number of the multiplier circuits actually required to be formed on the filter circuit.
With the increase in the transmission rate, however, the parallel operation of all the multiplier circuits is required due to the limited operating speed of each multiplier circuit. It will be necessary, for example, to form as many as 200 multiplier circuits. A simple digitization, therefore, constitutes a stumbling block to a higher transmission rate due to the increased circuit size of the multiplier circuits.
According to an aspect of the present invention, there is provided a digital signal transmission system in which the requirement for a high transmission rate can be met without increasing the circuit size of the digital orthogonal modulator/demodulator.
According to another aspect of the invention, there is provided a digital signal communication system comprising a transmission circuit or a receiving circuit in which two types of signals are digitally transmitted by orthogonal modulation. In a digital signal communication system according to this invention, the transmission circuit includes an orthogonal modulator and a nonrecursive digital low-pass filter having the same frequency characteristic as a predetermined frequency characteristic of the output signal of the orthogonal modulator, and the receiving circuit includes an orthogonal demodulator and a nonrecursive digital low-pass filter having the same frequency characteristic as a predetermined frequency characteristic of the output signal of the orthogonal demodulator. The total number of taps required for determining the frequency characteristic of the nonrecursive digital low-pass filters is assumed to be H, and the series of the tap coefficients to be C1, C2, C3, . . . CH, where H is an arbitrary positive integer not less than 2. The nonrecursive digital low-pass filters have a first low-pass filter for filtering one of the two types of signals and a second low-pass filter for filtering the other type of the signals. The first low-pass filter has substantially one half of H taps including a series of tap coefficients C1, C3, C5, . . . C2R+1, and the second low-pass filter has substantially one half of the H taps including a series of tap coefficients C2, C4, C6, . . . ,C2R, where R is an arbitrary positive integer.
The use of tap coefficients meeting the above-mentioned condition can reduce the taps of the digital LPFs almost by one half. Specifically, the number of multiplier circuits required can be reduced as remarkably as by one half for a smaller circuit size.